Conventional semiconductor devices having integrated circuitry normally comprise a plurality of openings characterized as "vias," "contacts," or "windows," in a dielectric layer. These openings are normally filled with a conductive material having low resistivity, such as a metal or polysilicon, to provide electrical connection through the dielectric material. For example, in many MOSFET fabrication techniques, after formation of the source, drain and gate, a dielectric is deposited over the transistor and an opening created above some or all the source and drain regions. A conductive material, such as aluminum, is deposited within the opening to effect electrical contact with the source or drain region. Thus, the conductive material in the opening provides a path for electrical contact between the source or drain region and a conductive material on the upper surface of the dielectric layer. Multilevel integrated circuits comprise a plurality of dielectric layers having openings filled with conductive material which provides electrical contact between conductive runners or lines beneath and above the additional dielectric layers.
In order to satisfy increasingly higher density requirements, the dimensions of integrated circuits are continuously reduced and, hence, the line widths of the conductors decreased into the submicron range. While the conductors become narrower and narrower, the stresses imposed upon the conductive material increase, thereby resulting in a high failure rate. Many of these failures stem from defects or voids generated by stress migration as a result of thermal stresses caused by exposure at different temperatures. Other types of voids are generated by electromigration and during various production steps, such as etching. These voids, which can range from 0.1 microns to about 10 microns or more, ultimately lead to failures in narrow electrical lines by causing open circuits.
The detection of voids in metallization patterns is a recognized objective in the art. However, this objective constitutes a perplexing problem which is not easily attained. A conventional technique employed to detect voids in metallization patterns involves the use of a scanning electron microscope. This technique is extremely time consuming and normally requires about a day to check one device. Another method which has been employed to detect voids in metallization patterns is an indirect method based upon resistance measurements. However, since a detected higher resistance can be attributed to multiple underlying causes, this method of void detection is not accurate.
A recently developed technique for detecting stress-induced voids is disclosed by Smith et al., "Direct Measurement of Stress-Induced Void Growth by Thermal Wave Modulated Optical Reflectance Imaging" IEEE/RPS 1990, pages 200-208. Smith et al. reveal a technique characterized as "thermal wave" modulated optical reflectance imaging which nondestructively detects voids within metallization patterns with submicron resolution. The thermal wave technique involves utilizing a laser beam and analyzing the reflected periodic waves of heat or thermal waves. The disadvantages of the "thermal wave" technique are multiple. A fundamental disadvantage of the "thermal wave" technique stems from the necessity of employing reflected laser light, which limits the minimum size of a metal line that can be imaged to the laser light wave length. Since a He-N.sub.2 laser with a wave length of 628 nm is generally employed, the metal line width that can be imaged is restricted to about 0.6 microns. This constitutes a severe limitation on the "thermal wave" technique, since current technology involves metal lines less than 0.5 microns. Moreover, the "thermal wave" technique is highly cumbersome and cannot be practically employed in a manufacturing environment.
Apart from the previously mentioned scanning electron microscope and thermal wave technique, we are not aware of any method conventionally employed in the semiconductor industry to detect voids in metallization patterns. The disadvantages of such previously mentioned detection technique leaves the problem of detecting voids in metallization patterns acute, particularly in manufacturing high and ultra high density semiconductor devices.
A prior art non-destructive technique for detecting defects and electrical discontinuities comprises the application of a current to a test piece or section. A rise in temperature or "hot spot" occurs in the vicinity of the defect or discontinuity which can be visually detected.
Nishioka, U.S. Pat. No. 4,431,967, discloses a method for detecting minute defects on a semiconductor chip by applying a current to generate a hot spot and observing the hot spot using an optical microscope and a nematic liquid crystal film. Gavrilin et al., U.S. Pat. No. 4,215,562, disclose a method for detecting surface and sub-surface flaws in a rolled product by high frequency heating to produce a temperature gradient wherein a change of color is observed in a indicator coating. Woodmansee, U.S. Pat. No. 3,511,086, discloses a method for detecting voids and other discontinuities in a substrate by applying a cholesteric liquid crystalline material, thermal cycling and observing a color response. Burgess et al., "Improved Sensitivity for Hot Spot Detection Using Liquid Crystals," IEEE/IRPS 1984, pages 119-121, disclose a method for detecting defects employing a nematic liquid crystalline material. Maley, U.S. Pat. No. 3,504,525, discloses a nondestructive infrared technique for detecting voids and inclusions in material. Hancock et al., U.S. Pat. No. 4,466,746, disclose a detection technique employing a boiling liquid to detect hot spots in electronic circuitry, such as printed circuit boards and metallization patterns. The use of an infrared microscope is also disclosed. U.S. Pat. No. 5,298,433 discloses a screening method for testing an interconnection on a semiconductor wafer by judging whether or not the electrical characteristics of each chip area are acceptable through a die sort test and remedying an integrated circuit in a chip by means of the redundant circuit prior to assembly in an integrated circuit device.
A recent development in integrated circuitry comprises the use of a barrier layer or layers under and/or above the metallization layer for various reasons. One such device is disclosed by Lai et al. in U.S. Pat. No. 5,229,311. With reference to FIG. 1, the semiconductor device disclosed by Lai et al. comprises a substrate 13 provided with source region 11 and drain region 10, separated by field oxide isolation regions 15. Above channel region 12 is formed a first polysilicon layer which functions as a floating gate for the memory cell and a second polysilicon gate 17 which functions as a control gate separated by insulation 22, with 23 representing a thermally grown oxide layer over the source/drain and polygate surfaces. A planarizing dielectric film 18 is then deposited on the thermal oxide by a conventional chemical vapor deposition technique. A barrier metal layer 19 is then formed. Barrier metal layer 19 can comprise titanium or a titanium rich compound such as titanium nitride or titanium-tungsten. An aluminum metallization or bit line 20 is then formed and, subsequently, insulation layer 21 provided.